This invention pertains to ferroelectric capacitors and integrated circuit memory devices, and, more particularly, to textured electrodes for ferroelectric capacitors.
The term xe2x80x9ctexturexe2x80x9d or xe2x80x9ctexturedxe2x80x9d generally refers to the crystallographic orientation of the material being discussed, and is not to be confused with the surface smoothness of the material. Specifically, the texture of the electrode and dielectric material being discussed refers to the crystallographic orientation of the material in the xe2x80x9cZ-axisxe2x80x9d and does not generally describe the orientation of the material in the X or Y axes (parallel to the surface of the integrated circuit). In fact, the grain structure of the material is generally random in the X or Y axes, yet it is ordered in the preferred orientation in the Z-axis of the material for maximizing electrical performance as is disclosed in greater detail below with respect to the description of the invention.
One possibility for improving the electrical performance of a ferroelectric memory is by texturing the ferroelectric dielectric material. Referring now to FIG. 1, a typical prior art ferroelectric capacitor 10 is shown including a substrate 12, a bottom electrode 14, a Perovskite ferroelectric dielectric layer 16 such as Pb(Zr1-XTiX)O3 (xe2x80x9cPZTxe2x80x9d), and a top electrode 18. The bottom electrode layer 14 and top electrode layer 18 are typically platinum or iridium. It is desirable for ferroelectric dielectric layer 16 to have a texture that maximizes electrical performance, and not a random grain structure. The use of a textured dielectric layer helps to maximize signal strengths and minimize operating voltage distribution since the polarization vector of all of the grains in the layer are oriented in the same direction. This is especially important if, as is required in integrated circuit memories, the capacitor area is very small ( less than 1 xcexcm2) and the number of grains is also small ( less than 50 grains). Randomly distributed grain orientation in the Z-axis of the dielectric film substantially affects signal strength and electrical memory performance.
Presently available bottom electrode structures and processing methods do not support a textured PZT ferroelectric dielectric layer and therefore process control and narrow single-bit signal distributions cannot be achieved for high density memories. With randomly oriented materials, the distribution in bit signals is large for capacitor sizes approaching the grain size of the PZT layer (typically 0.1-0.3 xcexcm) since the switchable polarization is a vector property linked with specific crystal directions.
In particular, it has also been found that it is difficult to maintain good PZT crystallographic texture on iridium metal bottom electrodes. Iridium metal is oxidized when it is exposed to air or oxygen-containing environments. Currently, after iridium deposition, the iridium is typically exposed to air, resulting in a surface layer of IrOX that does not provide the proper template for textured PZT growth. While it may be possible to prevent iridium oxidation by directly depositing the PZT after iridium deposition and avoiding a vacuum break, the oxygen present in the PZT and the atmosphere used to deposit PZT can also cause iridium oxidation in an uncontrolled manner.
Exposure, therefore, of an iridium bottom electrode to atmosphere causes surface oxidation of the iridium. This surface oxidation causes an undesirable non-oriented PZT dielectric layer to be formed. Current platinum technology does not prevent oxygen diffusion through the bottom electrode. This, in turn, does not allow protection of contacts that lie below the bottom electrode in a capacitor-on-plug FRAM(copyright) memory architecture.
What is desired, therefore, is a bottom electrode structure for a ferroelectric capacitor that supports the growth of a properly textured ferroelectric dielectric film.
According to the present invention, a method is described for producing crystallographically textured electrodes for making ideally textured PZT capacitors for enhanced ferroelectric memory performance. The use of seed layers originating from hexagonal crystal structures with {0001} texture provides a template with a smooth surface for growth of {111} textured iridium, which exhibits the face-centered cubic (xe2x80x9cFCCxe2x80x9d) structure. This seeding technique results in {111} textured iridium with a small surface roughness relative to the film thickness. The highly textured iridium acts as a template for {111} textured PZT growth. Textured PZT exhibits enhanced switched polarization, reduced operating voltage and also improves the reliability of PZT capacitors used in FRAM(copyright) memory and other microelectronic devices.
One advantage of using iridium is that iridium provides a barrier against oxygen diffusion. When the PZT capacitor is formed on top of a tungsten, silicon, or other plug material, oxidation of the plug is ideally prevented (or at least limited) to avoid excessively high contact resistance between the plug and the capacitor. Capacitor-over-plug architectures are normally required for high density memories that incorporate small capacitors ( less than 1 xcexcm2). It is therefore desirable to maintain a textured PZT layer to have a maximum switching signal, low operating voltage and a narrow distribution in bit-to-bit response. With textured materials, all capacitors substantially exhibit the same switchable polarization since all the PZT grains exhibit the same texture.
During vapor phase deposition, materials with hexagonal crystal structures have a natural growth habit such that the basal plane, i.e., the {0001} plane, prefers to grow parallel to the surface of a planarized substrate. This growth habit results in the formation of {0001} textured films with smooth surfaces that terminate on the {0001} plane. This smooth {0001} lattice plane in turn provides an ideal growth surface for growth of a smooth subsequent layer. In addition, the basal planes of hexagonal structure materials are close-packed planes that provide for an excellent template for growth of {111} textured films exhibiting an FCC crystal structure. The {111} planes in the FCC structure are also close-packed planes. In fact, the only difference between hexagonal close-packed structures and face-centered cubic structures is the stacking sequence of the close-packed planes. ABC stacking is exhibited in FCC structures and AB stacking is exhibited in HCP structures. The FCC (111) plane can have a good lattice match with the HCP (0001) plane. A mismatch as large as 25% can be accommodated between the FCC (111) and HCP (0001) lattice while still assuring that the HCP (0001) lattice acts as a seed for textured growth of the FCC (111) lattice. The mismatch is given by:             2      ⁢              a        H              -                  2            ⁢              a        F                        2        ⁢          a      F      
where aH is the unit cell parameter for the hexagonal basal plane of the seed layer and aF is the unit cell parameter for the FCC electrode layer.
Since the HCP seed layer is textured, the lattice match of the FCC and HCP structures introduce a texture of the FCC material. The lattice match between the FCC (111) and HCP (0001) planes is confined within a single grain; therefore the FCC layer exhibits a {111} texture perpendicular to the plane of the substrate, but the grains are randomly oriented with respect to relative rotations within the plane of the substrate.
Tetragonal seed layers that form a distorted hexagonal sub-lattice can also be used to achieve textured Ir films. Such films can be formed by using thermal oxidation or nitridation of smooth {0001} as-grown hexagonal metal films, resulting in alternative oxide and nitride based seed layers with smooth surfaces. These oxide and nitride seed layers can also be used to achieve better lattice matching with FCC electrodes and therefore result in improved texture of the FCC electrode film. Formation of compound hexagonal and tetragonal seed layers can also be achieved by deposition processing such as sputtering and MOCVD. An example of a tetragonal seed layer that can be formed by thermal oxidation is TiO2, which exhibits the rutile structure and a distorted hexagonal oxygen sub-lattice. Hexagonal Ti with an {0001} texture transforms to tetragonal TiO2 with a {100} texture. The FCC (111) lattice can have a good match with the tetragonal rutile (200) lattice provided that the lattice mismatch is less than 25%. The lattice mismatch in this case is given by                     2        ⁢                  c          T                    -                        2                ⁢                  a          F                                    2            ⁢              a        F              ⁢      xe2x80x83    ⁢  and  ⁢      xe2x80x83    ⁢                    a        T            -                                    3            2                          ⁢                  a          F                                              3          2                    ⁢              a        F            
where cT and aT are the unit cell parameters for the tetragonal seed layer and aF is the unit cell parameter for the FCC electrode layer.
Because of the natural growth habit of the hexagonal close-packed (xe2x80x9cHCPxe2x80x9d) structure of titanium, titanium growth with an {0001} texture provides for an excellent seed layer for the growth of {111} textured FCC iridium. Because of the strong growth habit of titanium, this seed layer can be grown on a variety of amorphous and crystalline substrates while still maintaining a high quality of {0001} texture. Because the {0001} titanium texture can be maintained on a variety of substrates, it provides for a universal seed layer that can be used on top of an interlevel dielectric, plug, and other barrier materials that are placed on top of the plug structure. In turn, the {0001} textured titanium can be thermally oxidized to form a stable oxide that also provides not only a thermally stable seed layer but also a smooth seed layer that allows the growth of {111} textured iridium that can act as a bottom electrode for textured PZT growth. The thermally oxidized titanium exhibiting a {100} textured rutile structure is ideally grown such that it exhibits a 200 X-ray diffraction (xe2x80x9cXRDxe2x80x9d) rocking-curve peak with a full width at half maximum (xe2x80x9cFWHMxe2x80x9d) of less than 5xc2x0. With such a seed layer, the iridium can be grown with a 111 rocking-curve FWHM of less than 5xc2x0, which is ideally required to achieve a high quality 111 PZT texture with a 111 rocking-curve of less than 5xc2x0 omega. Such a PZT texture is ideally needed to achieve the full performance benefits of the textured PZT. In order to achieve the high degree of iridium texture, the iridium is ideally deposited in a temperature range of 300 to 700xc2x0 C.
The method of the present invention includes a hexagonal close-packed seed layer, which is employed as-grown, oxidized or nitrided by thermal processing, with an FCC bottom electrode, and can be extended to other materials. Potential hexagonal metal seed layers include titanium, cobalt, zirconium and ruthenium, among other materials as is explained in greater detail below. The advantage of using ruthenium is that oxidation of ruthenium still results in a conducting layer.
Other hexagonal materials that can act as a seed layer include BN, AlN, GaN, InN, ZnO, and other wurtzite (or hexagonal) structure materials, as well as solid solutions or doped derivatives of these materials. For these materials, the anion sub-lattice provides the close-packed basal plane that provides the lattice match with the FCC close-packed (111) plane.
These can be formed by a variety of thin film deposition processes including sputtering and MOCVD. The advantage of using the wurtzite structure nitrides is that the seed layer can also provide additional protection against oxidation of the plug since it is known that certain nitrides are resistant to oxidation.
Other seed layer compounds having a hexagonal or tetragonal crystal structure that contains a hexagonal or distorted hexagonal sublattice can be used if that compound provides a lattice match with the iridium {111} plane within 25%. Additionally, other FCC electrode materials can be used in place of iridium and these include Pt, Pd, Ag, Au, Cu, and Ni, among other materials as is explained in further detail below.
The present invention also provides a means to prevent iridium oxidation and provides a means for textured PZT growth with a narrow rocking-curve FWHM. The iridium layer provides a barrier against oxygen diffusion, which can be used to prevent oxidation of conducting plugs in a FRAM(copyright) capacitor-over-plug ferroelectric memory architecture.
Textured iridium with a 111 rocking-curve FWHM of less than 5xc2x0 is first deposited to a thickness of 1-100 nm. Without breaking vacuum, a platinum layer (1 to 50 nm thick) is deposited on top of the iridium. Because of the close lattice match and same FCC structure of platinum and iridium, the platinum grows with a {111} texture that has a 111 rocking-curve FWHM similar to iridium. Since the platinum does not oxidize when exposed to air and oxidizing environments, the Pt/Ir electrode is stable against oxidation. Textured PZT can easily be grown on the platinum layer when the platinum has a 111 rocking-curve FWHM of less than 5xc2x0. The high degree of PZT texture ensures high performance ferroelectric properties for FRAM(copyright) memory applications. An additional advantage is the PZT provides a narrow distribution in the signal sensed from bits comprising the FRAM memory.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention, which proceeds with reference to the accompanying drawings.